1. Field of the Invention
The invention relates to semiconductor package technology, and in particular to a chip package and methods for forming the same.
2. Description of the Related Art
The chip packaging process is an important step in the fabrication of an electronic product. Chip packages not only protect the chips therein from outer environmental contaminants, but they also provide electrical connection paths between electronic elements inside and those outside of the chip packages.
Manufacturing processes of chip packages comprise dicing a wafer substrate, which is attached to a carrier wafer, into a plurality of chips. The carrier wafer and the chips thereon are then disposed on pins in deposition equipment. Next, the pins are lowered, such that the carrier wafer is completely loaded on a work surface of the equipment to perform a deposition process on the chips, such as depositing an oxide layer on the chips.
However, vacuum gaps are formed between portions of the carrier wafer, which are previously supported by the pins of the deposition equipment, and the underlying pins. Namely, the portions of the carrier wafer previously supported by the pins are not in contact with the work surface of the equipment. Therefore, the overlying chips adjacent to the vacuum gaps have poor thermal conduction during the deposition process. As a result, the thickness of the oxide layer, which is subsequently formed on the chips, is non-uniform, thereby affecting the quality of the chip packages.
Thus, there exists a need in the art for development of a chip package and methods for forming the same capable of mitigating or eliminating the aforementioned problems.